CD54/74HC123, CD54/74HCT123, CD74HC423, CD74HCT423

High-Speed CMOS Logic Dual Retriggerable Monostable Multivibrators with Resets

Features

• Overriding Reset Terminates Output Pulse

• Triggering From the Leading or Trailing Edge

• Q and Q Buffered Outputs

• Separate Resets

• Wide Range of Output-Pulse Widths

• Schmitt Trigger on Both A and B Inputs

• Fanout (Over Temperature Range)

- Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads

- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads

• Wide Operating Temperature Range . . . -55℃ to 125℃

• Balanced Propagation Delay and Transition Times

• Significant Power Reduction Compared to LSTTL Logic ICs

• HC Types

- 2V to 6V Operation

- High Noise Immunity: N_IL = 30%, N_IH = 30%of V_CC at V_CC = 5V

• HCT Types

- 4.5V to 5.5V Operation

- Direct LSTTL Input Logic Compatibility, V_IL= 0.8V (Max), V_IH = 2V (Min)

- CMOS Input Compatibility, I_l ≤ 1µA at V_OL, V_OH

Description

The ’HC123, ’HCT123, CD74HC423 and CD74HCT423 are dual monostable multivibrators with resets. They are all retriggerable and differ only in that the 123 types can be triggered by a negative to positive reset pulse; whereas the 423 types do not have this feature. An external resistor (R_X) and an external capacitor (C_X) control the timing and the accuracy for the circuit. Adjustment of Rx and C_X provides a wide range of output pulse widths from the Q and Q terminals. Pulse triggering on the A and B inputs occur at a particular voltage level and is not related to the rise and fall times of the trigger pulses

Once triggered, the output pulse width may be extended by retriggering inputs A and B. The output pulse can be terminated by a LOW level on the Reset (R) pin. Trailing edge triggering (A) and leading edge triggering (B) inputs are provided for triggering from either edge of the input pulse. If either Mono is not used each input on the unused device (A, B, and R) must be terminated high or low.

The minimum value of external resistance, Rx is typically 5kΩ. The minimum value external capacitance, CX, is 0pF. The calculation for the pulse width is tW = 0.45 R_XC_X at V_CC = 5V.

Absolute Maximum Ratings

DC Supply Voltage, V_CC . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7V

DC Input Diode Current, I_IK

For V_I < -0.5V or V_I > V^CC + 0.5V. . . . . . . . . . . . . . . . . . . . . .±20mA

DC Output Diode Current, I_OK

For V_O < -0.5V or V_O > V_CC + 0.5V . . . . . . . . . . . . . . . . . . . .±20mA

DC Output Source or Sink Current per Output Pin, I_O

For V_O > -0.5V or V_O < V_CC + 0.5V . . . . . . . . . . . . . . . . . . . .±25mA

DC V_CC or Ground Current, I_CC or I_GND . . . . . . . . . . . . . . . . . .±50mA

Operating Conditions

Temperature Range (T_A) . . . . . . . . . . . . . . . . . . . . . -55℃ to 125℃

Supply Voltage Range, V_CC

HC Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2V to 6V

HCT Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5V to 5.5V

DC Input or Output Voltage, V_I , V_O . . . . . . . . . . . . . . . . . 0V to V_CC

Input Rise and Fall Time

2V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000ns (Max)

4.5V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500ns (Max)

6V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400ns (Max)

Thermal Information

Package Thermal Impedance, θ_JA (see Note 1):

E (PDIP) Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67℃/W

M (SOIC) Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73℃/W

NS (SOP) Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64℃/W

PW (TSSOP) Package . . . . . . . . . . . . . . . . . . . . . . . . . 108℃/W

Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . 150℃

Maximum Storage Temperature Range . . . . . . . . . . -65℃ to 150℃

Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300℃

(SOIC - Lead Tips Only)

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

NOTE: 1. The package thermal impedance is calculated in accordance with JESD 51-7.

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