DIGITAL SIGNAL PROCESSORS
*Powerful 16-Bit TMS320C5x CPU
*20-, 25-, 35-, and 50-ns Single-Cycle
Instruction Execution Time for 5-V Operation
*25-, 40-, and 50-ns Single-Cycle Instruction
Execution Time for 3-V Operation
*Single-Cycle 16 × 16-Bit Multiply/Add
*224K × 16-Bit Maximum Addressable
External Memory Space (64K Program, 64K
Data, 64K I/O, and 32K Global)
*2K, 4K, 8K, 16K, 32K × 16-Bit Single-Access
On-Chip Program ROM
*1K, 3K, 6K, 9K × 16-Bit Single-Access
On-Chip Program/Data RAM (SARAM)
*1K Dual-Access On-Chip Program/Data
RAM (DARAM)
*Full-Duplex Synchronous Serial Port for
Coder/Decoder Interface
*Time-Division-Multiplexed (TDM) Serial Port
*Hardware or Software Wait-State Generation Capability
*On-Chip Timer for Control Operations
*Repeat Instructions for Efficient Use of Program Space
*Buffered Serial Port
*Host Port Interface
*Multiple Phase-Locked Loop (PLL)
Clocking Options (×1, ×2, ×3, ×4, ×5, ×9 Depending on Device)
*Block Moves for Data/Program Management
*On-Chip Scan-Based Emulation Logic
*Boundary Scan
*Five Packaging Options
– 100-Pin Quad Flat Package (PJ Suffix)
– 100-Pin Thin Quad Flat Package (PZ Suffix)
– 128-Pin Thin Quad Flat Package (PBK Suffix)
– 132-Pin Quad Flat Package (PQ Suffix)
– 144-Pin Thin Quad Flat Package (PGE Suffix)
*Low Power Dissipation and Power-Down Modes:
– 47 mA (2.35 mA/MIP) at 5 V, 40-MHz Clock (Average)
– 23 mA (1.15 mA/MIP) at 3 V, 40-MHz Clock (Average)
– 10 mA at 5 V, 40-MHz Clock (IDLE1 Mode)
– 3 mA at 5 V, 40-MHz Clock (IDLE2 Mode)
– 5 µA at 5 V, Clocks Off (IDLE2 Mode)
*High-Performance Static CMOS Technology
*IEEE Standard 1149.1† Test-Access Port (JTAG)
description
The TMS320C5x generation of the Texas Instruments (TITM) TMS320 digital signal processors (DSPs) is fabricated with static
CMOS integrated circuit technology; the architectural design is
based upon that of an earlier TI DSP, the TMS320C25. The
combination of advanced Harvard architecture, on-chip peripherals,
on-chip memory, and a highly specialized instruction set is the
basis of the operational flexibility and speed of the ’C5x‡
devices. They execute up to 50 million instructions per second
(MIPS).
The ’C5x devices offer these advantages:
- Enhanced TMS320 architectural design for increased performance and
versatility
- Modular architectural design for fast development of spin-off
devices
- Advanced integrated-circuit processing technology for increased
performance
- Upward-compatible source code (source code for ’C1x and ’C2x DSPs is upward compatible with ’C5x
DSPs.)
- Enhanced TMS320 instruction set for faster algorithms and for
optimized high-level language operation
- New static-design techniques for minimizing power consumption and
maximizing radiation tolerance
TMS320C50, TMS320LC50, TMS320C51, TMS320LC51, TMS320C53, TMS320LC53
PQ PACKAGE
(TOP VIEW)
absolute maximum ratings over operating ambient-air temperature
range (unless otherwise noted) (’320C5x only)†
Supply voltage range, VDD (see Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . .– 0.3 V to 7 V
Input voltage range, VI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . .– 0.3 V to 7 V
Output voltage range, VO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . .– 0.3 V to 7 V
Operating ambient temperature range, TA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . –40°C to 85°C
Operating case temperature, TC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . 0°C to 85°C
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . – 55°C to 150°C
† Stresses beyond those listed under “absolute maximum ratings” may
cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other
conditions beyond those indicated under “recommended operating
conditions” is not implied. Exposure to absolute-maximum-rated
conditions for extended periods may affect device reliability.
NOTE 3: All voltage values are with respect to VSS.
recommended operating conditions (’320C5x only)
| MIN NOM MAX | UNIT |
| VDD Supply voltage | 4.75 5 5.25 | V |
| VSS Supply voltage | 0 | V |
| VIH High-level input voltage | X2/CLKIN, CLKIN2 | 3 VDD+0.3 | V |
| CLKX, CLKR, TCLKX, TCLKR | 2.5 VDD+0.3 | V |
| All other inputs | 2 VDD+0.3 | V |
| VIL Low level input voltage | X2/CLKIN, CLKIN2, CLKX, CLKR, TCLKX, TCLKR | – 0.3 0.7 | V |
| All other inputs | – 0.3 0.8 | V |
| IOH High-level output current (see Note 4) | – 300‡ | µA |
| IOL Low-level output current | 2 | mA |
| TC Operating case temperature | 0 85 | °C |
| TA Operating ambient temperature | –40 85 | °C |
‡ This IOH can be exceeded when using a 1-kΩ pulldown resistor on the TDM
serial port TADD output; however, this output still meets VOH specifications under these conditions.
NOTE 4: Figure 9 shows the test load circuit and Figure 10 and
Figure 11 show the voltage reference levels.
