64K (8K x 8) Parallel EEPROM with Page Write and Software Data
Protection AT28C64B
Features
• Fast Read Access Time – 150 ns
• Automatic Page Write Operation
– Internal Address and Data Latches for 64 Bytes
• Fast Write Cycle Times
– Page Write Cycle Time: 10 ms Maximum (Standard)
2 ms Maximum (Option – Ref. AT28HC64BF Datasheet)
– 1 to 64-byte Page Write Operation
• Low Power Dissipation
– 40 mA Active Current
– 100 µA CMOS Standby Current
• Hardware and Software Data Protection
• DATA Polling and Toggle Bit for End of Write Detection
• High Reliability CMOS Technology
– Endurance: 100,000 Cycles
– Data Retention: 10 Years
• Single 5V ±10% Supply
• CMOS and TTL Compatible Inputs and Outputs
• JEDEC Approved Byte-wide Pinout
• Industrial Temperature Ranges
• Green (Pb/Halide-free) Packaging Option
1. Description
The AT28C64B is a high-performance electrically-erasable and
programmable readonly memory (EEPROM). Its 64K of memory is
organized as 8,192 words by 8 bits. Manufactured with Atmel’s
advanced nonvolatile CMOS technology, the device offers access
times to 150 ns with power dissipation of just 220 mW. When the
device is deselected, the CMOS standby current is less than 100 µA.
The AT28C64B is accessed like a Static RAM for the read or write
cycle without the need for external components. The device contains
a 64-byte page register to allow writing of up to 64 bytes
simultaneously. During a write cycle, the addresses and 1 to 64
bytes of data are internally latched, freeing the address and data
bus for other operations. Following the initiation of a write
cycle, the device will automatically write the latched data using
an internal control timer. The end of a write cycle can be detected
by DATA POLLING of I/O7. Once the end of a write cycle has been
detected, a new access for a read or write can begin.
Atmel’s AT28C64B has additional features to ensure high quality and
manufacturability. The device utilizes internal error correction
for extended endurance and improved data retention characteristics.
An optional software data protection mechanism is available to
guard against inadvertent writes. The device also includes an extra
64 bytes of EEPROM for device identification or tracking.
2. Pin Configurations
| Pin Name | Function |
| A0 - A12 | Addresses |
| CE | Chip Enable |
| OE | Output Enable |
| WE | Write Enable |
| I/O0 - I/O7 | Data Inputs/Outputs |
| NC | No Connect |
| DC | Don’t Connect |
2.1 28-lead PDIP, 28-lead SOIC Top View
2.2 32-lead PLCC Top View
Note: PLCC package pins 1 and 17 are Don’t Connect.
2.3 28-lead TSOP Top View
3. Block Diagram
4. Absolute Maximum Ratings*
Temperature Under Bias................................ -55°C to
+125°C
Storage Temperature ..................................... -65°C to
+150°C
All Input Voltages
(including NC Pins)
with Respect to Ground ...................................-0.6V to
+6.25V
All Output Voltages
with Respect to Ground .............................-0.6V to VCC +
0.6V
Voltage on OE and A9
with Respect to Ground ...................................-0.6V to
+13.5V
*NOTICE: Stresses beyond those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or any
other conditions beyond those indicated in the operational sections
of this specification is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect device
reliability
