FAN7530

Critical Conduction Mode PFC Controller

Features „

• Low Total Harmonic Distortion (THD) „
• Precise Adjustable Output Over-Voltage Protection „
• Open-Feedback Protection and Disable Function „
• Zero Current Detector „
• 150µs Internal Start-up Timer „
• MOSFET Over-Current Protection „
• Under-Voltage Lockout with 3.5V Hysteresis „
• Low Start-up (40µA) and Operating Current (1.5mA) „
• Totem Pole Output with High State Clamp „
• +500/-800mA Peak Gate Drive Current „
• 8-Pin DIP or 8-Pin SOP

Applications „

• Adapter „
• Ballast „
• LCD TV, CRT TV „
• SMPS

Related Application Notes „

• AN-6027 - Design of Power Factor Correction Circuit Using FAN7530

Description

The FAN7530 is an active power factor correction (PFC) controller for boost PFC applications that operates in critical conduction mode (CRM). It uses the voltage mode PWM that compares an internal ramp signal with the error amplifier output to generate MOSFET turn-off signal. Since the voltage mode CRM PFC controller does not need rectified AC line voltage information, it saves the power loss of the input voltage sensing network necessary for the current mode CRM PFC controller.

FAN7530 provides many protection functions, such as over voltage protection, open-feedback protection, overcurrent protection, and under-voltage lockout protection. The FAN7530 can be disabled if the INV pin voltage is lower than 0.45V and the operating current decreases to 65µA. Using a new variable on-time control method, THD is lower than the conventional CRM boost PFC ICs.

Absolute Maximum Ratings

The “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The parametric values defined in the Electrical Characteristics tables are not guaranteed at the absolute maximum ratings. TA=25°C, unless otherwise specified.

Typical Application Diagrams

Figure 1. Typical Boost PFC Application

Internal Block Diagram

Figure 2. Functional Block Diagram of FAN7530

Pin Assignments

Figure 3. Pin Configuration (Top View)

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